1. Field of the Invention
This invention relates to logic circuits and more particularly to an arrangement for enhancing or accelerating the switching operation in a variety of well known logic circuits.
2. Background Information
In order to provide background for an appreciation of the present invention, and particularly for an understanding of the several contexts which form the setting for the invention, reference may be made to the following U.S. Pat. Nos. 3,358,154, 3,505,535, 3,549,899, 3,564,281, 3,699,355 and 3,914,628.
Of particular interest with respect to the present invention are two of the aforesaid patents, namely U.S. Pat. Nos. 3,505,535 and 3,358,154. The former is of special note because it relates to an improvement on a particular form of high speed logic circuitry, known in the art as current switching. This technique can be appreciated by reference to U.S. Pat. No. 2,964,652 to H. S. Yourke, the disclosed circuit of which possesses superiority with respect to most other switching circuits, particularly in respect to both speed and stability. In this so-called current switch, a constant current is supplied and is switched either through one or more logic transistors or through a grounded base (reference) transistor, depending upon the potential levels of the input signals at the bases of the logic or signal transistors relative to the reference potential at the grounded base. Since the current which flows through the collector load resistors is substantially constant and predetermined, the circuit parameters may be selected so as to limit the potential swing of the collectors and thereby maintain the transistors out of saturation so as to enhance the switching speed.
The improvement provided by U.S. Pat. No. 3,505,535 on the current switch mode of operation involves the inclusion of a non-linear network at the output of the logic or signal transistors, this network including a load transistor which essentially supplies the non-linear impedance required. The operation of the improved circuit of U.S. Pat. No. 3,505,535 is such that when a logic transistor turns on, the input impedance of the load transistor, unlike a conventional linear load resistor, is reduced to an extremely low value, although providing an extremely high impedance under cut-off conditions.
Whatever the merits of the improved circuit of U.S. Pat. No. 3,505,535 it will become apparent hereinafter that its superficially similar construction totally differs from that of the present invention.
Another pertinent reference, already cited above, is U.S. Pat. No. 3,358,154 which discloses an arrangement for high speed logic gates in which a "tri-state" or three state configuration is provided in its FIG. 2. This circuit also bears a resemblance to the circuit configuration of applicant's invention; however, its operation is fundamentally different in that any improvement in switching speed is gained at the expense of power; moreover the nature of the circuit in U.S. Pat. No. 3,358,154 is such that what may be considered an enhancement transistor operates in an entirely different mode. Thus, that particular enhancement transistor is required to operate in the opposite state from the logic or signal transistors, and during any transient is always being turned off when the signal or logic transistors are being turned on, or vice versa.
It is therefore a primary object of the present invention to provide a means for enhancing logic circuit performance and, more particularly, to enhance the operating speed of a variety of logic circuits.
A more specific object is to enhance the switching speed of a logic circuit by capitalizing on the delay or lag time involved in the switching of an enhancement device connected to a node common to the logic circuit and the associated enhancement device.
The achievement of switching speed enhancement lies in the recognition that the coupling of an enhancement transistor to the output of a high speed logic device can be so arranged that the discharge of current from the enhancement transistor, or equivalent device, can be judiciously exploited during the transition period of the output signal.